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System Signal/Power Integrity Engineer

System Signal/Power Integrity Engineer

CompanyBroadcom Limited
LocationSan Jose, CA, USA, Fort Collins, CO, USA
Salary$141000 – $225000
TypeFull-Time
DegreesBachelor’s, Master’s, PhD
Experience LevelSenior, Expert or higher

Requirements

  • BS +8yrs, MS +6 yrs or PhD +3yrs Electrical Engineering or Physics
  • Experience in one or more of: Signal integrity for high-speed digital applications, Electromagnetic transmission line theory, Microwave theory, Numerical Field solver theory, Power integrity, IC package design, Photonics

Responsibilities

  • Support high data rate SerDes applications – up to 112Gbps NRZ and 224G PAM4 systems
  • System level Signal and Power Integrity design trade-offs and debug
  • Collaborate with package, PCB, and silicon designers to complete measurement-simulation correlation projects
  • Develop models with electromagnetic field solvers: primarily with Ansys HFSS and electronic suite
  • Ability to understand laminate design and fabrication techniques and limitations for both package and PCB designs
  • Evaluate system, PCB and package material and connector solutions for future designs
  • Simulate schematic models and environments within Keysight ADS
  • Ensure and know trade-offs for the accuracy of models (3D/2.5D/2D) used for design simulations
  • Perform and develop VNA/TDR (50GHz+) measurement techniques and correlate with models and simulations
  • Provide feedback and learnings from measurement-simulation correlation investigations to improve best practices for modeling and simulations
  • Capture high fidelity lab measurements to be used for correlation and debug purposes
  • Understand and apply high speed data communications, transmission-line and electromagnetic-field theory, numerical analysis, VNA/TDR measurements, bit-by-bit and Statistical simulators for serial data (SerDes) links, insertion loss, return loss, crosstalk, BER, jitter, and statistical eye diagrams
  • Work in either time domain or frequency domain
  • Phase noise analysis as it applies to PLL’s, reference clocks, SerDes TX-RX links
  • Jitter sensitivity measurement and analysis for SerDes IP
  • Organize and manage multiple projects
  • Develop, clearly and effectively document, and track project plans
  • Effectively communicate complex concepts in conversation, presentations and written documents
  • Determine and document applicable requirements for ASIC package and PCB designs, drawing from industry standards, customer requirements, and/or APD Broadcom’s internal performance goals
  • Collaborate with Package and PCB Engineers to fulfill System SI requirements, while balancing objectives (reliability, cost, complexity, etc.)
  • Pre-layout and post-layout modeling and simulation to support package and PCB engineering for signal integrity
  • Document and deliver SI models with supporting documentation to customer and internal engineers
  • Support customer analysis and debug efforts related to our deliverables
  • Understanding of optical/electrical engine concepts and theory of operation, CWDM, OMA, etc.
  • Familiarity with optical channel impairments such as chromatic dispersion (CD) and four-wave mixing (FWM)
  • Power Integrity Concepts: PDN impedance analysis and design, ultra-low impedance measurements, understanding of SMT capacitor performance metrics, use of CPA and/or SI-Wave for PDN simulations.

Preferred Qualifications

  • Matlab (desired)
  • Cadence APD/Allegro (desired)
  • Other layout tools (desired)
  • Linux (desired)
  • Keysight AEL (desired)
  • Perl (desired)