Staff Engineer – High Speed Analog Design
Company | Samsung |
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Location | San Jose, CA, USA |
Salary | $157000 – $243000 |
Type | Full-Time |
Degrees | Bachelor’s, Master’s, PhD |
Experience Level | Senior, Expert or higher |
Requirements
- BS with 10+ years or MS with 8+ years of experience or PhD with 5+ years in semiconductor field experience preferred.
- At least 5 years of experience in designing Si-based high speed circuit, including but not limited to PLL/DLL, CDR, RO/LC oscillators, regulators, TIA, limiting amplifiers, VGAs and digitally-assisted analog techniques.
- Deep understanding of impedance matching, return loss, phase noise, jitter analysis, budgeting and feedback loop dynamics.
- Production experience with one or more of the above-mentioned blocks.
- Proficiency in analog/mixed-signal circuit design, simulation and analysis, Experience with LC and RO VCO design. Good knowledge of band gaps, bias, op-amps, LDOs, feedback and compensation techniques as well as digitally assisted analog circuit techniques.
- Lab and ATE test plans, measurement for characterization, and volume production.
- Proficient in using Cadence, Synopsys and Siemens design tools, such as Virtuoso, Hspice, StarRC, Calibre etc.
- Hands-on experience in testing and characterization.
- Attention to details, exceptional focus on understanding the problems at hand and ensure thoroughness in problem-solving.
- Good written and verbal communication skills, with outstanding teamwork capabilities.
- Self-motivated with a growth mindset.
- Inclusive, adapt your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
Responsibilities
- High speed analog/mixed-signal circuit design, simulation and layout.
- Pre-layout and post-layout simulation and verification.
- Parasitic extraction and post-layout simulation.
- Top level spice and mixed-mode simulations to validate top level integration.
- Writing descriptions, detailed information and test plan of the designed blocks.
- Analyzing and interpreting test results.
Preferred Qualifications
- Experience with LC and RO VCO design. Good knowledge of band gaps, bias, op-amps, LDOs, feedback and compensation techniques as well as digitally assisted analog circuit techniques.