Sr. Staff IC Package Design Engineer – Packaging Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Senior, Expert or higher |
Requirements
- Knowledge for wafer bump, assembly, substrate technology, material trends and flip-chip package designs
- Hands-on experience with Cadence APD/SIP or Mentor Expedition/Xpedition
- Good EE fundamentals and solid signal and power integrity fundamentals
- Experience/knowledge in the packaging technology including substrate, bump and assembly process
- Experience in package design, design for manufacturing review
- Familiar with layout review tools such as Valor or Calibre
- Excellent communication and organizational skills
Responsibilities
- Explore and recommend the packaging solutions and define POR for QCOM’s multi-chip module designs
- Facilitate product package risk assessment, mitigation plans, and establishing best known processes methodology to ensure robust package quality, reliability, and manufacturing yield
- Coordinate technical development for new design attributes across partner teams from design to manufacturing (bump and assembly process and substrate technology)
- Drive DFM/DFR/DFT, and TV design to identify the critical process window and material attributes.
Preferred Qualifications
- Experience preferred in schematic capture, layout and design using Cadence Allegro Schematic Design Entry (Concept HDL) design tools is a plus