Sr. Staff Formal Verification Engineer

BS degree in electrical engineering, or related fields, or equivalent practical experience; advance degrees (MS or PhD) is a plus
10+ years in ASIC verification with 5+ years focused on formal verification methods
Mastery of SystemVerilog Assertions (SVA) and formal property verification
Proficient on at least one popular formal verification tools in the industry (JasperGold, VC Formal, etc.)
Strong analytical skills and attention to detail when debugging complex issues
Good scripting skills for flow automation (tcl, python, etc.)
Good written and oral communication skills
Must be authorized to work in the United States or Canada

Verify hardware features of Language Process Unit (LPU)
Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions
Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities
Debug findings and collaborate with stakeholders in an efficient manner
Support silicon bring-up and debug using formal methods where it applies
Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency
Train and coach junior engineers on formal techniques and best practices; Help on methodology/FAQ documentation
Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads

Proven success in full-cycle formal sign-off for complex compute blocks
Expertise in formal apps: sequential equivalence checks, datapath, connectivity, etc.
Deep understanding of LPU or GPU architecture/design