Sr S/I Engineer – Hardware
| Company | Palo Alto Networks |
|---|---|
| Location | Santa Clara, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Senior |
Requirements
- Strong background in hands-on design and validation of high-speed PCB and ASIC package development
- Power integrity design and analysis and well versed in PI simulation tool such as PowerSI/DC, etc.
- Working experience with high speed NRZ and PAM4 Serdes
- Self-motivated with demonstrated teamwork and communication skills; ability to drive outcomes with both vendors and internal teams
- Out of the box thinking with the strong desire to innovate are essential
- Strong EM knowledge and in-depth expertise of EM simulation tools such as HFSS/PowerDC-SI/ADS/SiSoft
- Familiar with PCB fabrication process, dielectric material and stackup design
- Solid knowledge of the IEEE 802.3/ OIF specifications and COM simulations
- Strong lab skills and measurement experience are required (VNA, TDR, Real Time Scope, Sampling scope, BERT)
- Demonstrated ability in troubleshooting and failure analysis
- Ability to contribute on multiple projects and work in a dynamic, collaborative environment
Responsibilities
- Collaborate with a cross-functional team including: ASIC, Board design, PCB layout, Operations supply base management, Platform Software
- Evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability
- Contribute to ASIC package design for SI
- Model complex 3-dimensional structures in field simulation software
- Simulate Channel Analysis for high speed serdes and memory interfaces
- Design and analyze high-speed serial links (56G and beyond) and their compliance to internal specs and standards
- Create and verify module/package and PCB layout rules: perform pre- and post-route signal integrity analysis of ASIC and multi-chip-module designs
- Model and analyze power delivery networks for ASIC/package/module and PCB
- Create SI test plan for coverage of all serdes, memory, and external IO interfaces
- Drive creation and implementation for required test infrastructure (tools, scripts, etc.) with external vendors and internal software teams
- Perform lab measurements for design validation and simulation correlations
- Drive methodology enhancements and automation – improving performance and efficiency
- Mentor junior engineers and interns
Preferred Qualifications
- Knowledge of optical transceivers highly desired