Sr Principal Superconducting Circuit Design Engineer
Company | Northrop Grumman |
---|---|
Location | Baltimore, MD, USA |
Salary | $127000 – $190600 |
Type | Full-Time |
Degrees | Bachelor’s, Master’s, PhD |
Experience Level | Senior, Expert or higher |
Requirements
- BS in electrical engineering, computer engineering, physics, or a closely related field, with 8 years of experience, or MS degree with 6 years of experience, or PhD with 3 years of experience.
- Very strong attention to detail and organization.
- Mastery level experience with Cadence Virtuoso or similar IC design software.
- Experience with Linux infrastructure setup and PDK.
- Experience with 2D and 3D EM solving software such as ADS and HFSS.
- Strong problem solving, analytical, written, and oral communication skills.
- Able to collaborate with multiple team members and stakeholders to complete chip leadership tasks.
- Ability to independently take concepts and derive action items to complete assigned tasks with minimal guidance.
- Experience in mentoring junior designers.
- Can identify, provide, and own long term and long-lasting solutions for gaps in the design team.
- Able to obtain and maintain TS/SCI Clearance with Polygraph. US Citizenship is a requirement for this.
- Willing to work full-time on site in Baltimore Maryland.
Responsibilities
- Learn/build upon superconducting, quantum, design, and RF EM simulation techniques.
- Lead ASIC chip designs to product owner specification.
- Document and present weekly reports on design task status.
- Continue to learn and develop in a unique and interesting environment.
- Contribute to knowledge transfer to invest in building up junior designers.
Preferred Qualifications
- Working knowledge of the IC design flow including schematic capture, simulation, and layout.
- An interest in superconductivity and advanced computing technology.
- Experience with Python.
- Experience in semiconductor fabrication, testing, and/or novel idea creation.
- Experience in small to medium size team leadership.
- Experience in PDK coordination and Linux infrastructure setup and maintenance.
- Active TS/SCI Clearance with Polygraph