Sr Principal ASIC Design Engineer – Netsec

Sr Principal ASIC Design Engineer – Netsec

Requirements

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred)
• 15+ years of hands-on front-end ASIC design experience, with significant ownership of multiple complex modules or subsystems from specification through mass production silicon
• Expert-level proficiency in SystemVerilog RTL design
• Deep and demonstrable strength in digital logic design fundamentals, including state machines, synchronous and asynchronous FIFO design, flow control mechanisms (e.g., ready/valid, credits, backpressure), and the understanding and avoidance of head-of-line blocking and deadlock situations in complex datapaths
• Expertise in defining micro-architecture from high-level requirements for large and intricate digital blocks
• Advanced debugging skills across various verification platforms and silicon
• Strong command of timing, power, and area analysis, with proven ability to analyze reports, identify critical paths, and drive RTL changes to meet targets effectively
• Proficiency in scripting (Python, C/C++, Perl, bash, or tcsh) for automation and analysis
• Excellent technical leadership, collaboration, and written/verbal communication skills, including the ability to clearly explain complex design concepts and methodologies
• Strong networking or cybersecurity domain knowledge
• Extensive experience with relevant protocols/technologies (e.g., PCIe, Ethernet IEEE 802.3, search-algorithm accelerators, ARM AMBA buses like AXI/AHB/APB, cryptographic algorithms)
• Hands-on silicon validation and lab bring-up experience

Responsibilities

• Define and document clear, comprehensive design and micro-architecture specifications for complex digital logic blocks and subsystems
• Design high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets, with particular emphasis on complex datapath designs
• Lead debug efforts across simulation, emulation, formal methods, and silicon bring-up environments
• Partner closely with verification engineers to define test plans, debug complex scenarios, close coverage, and add design-for-debug features
• Collaborate effectively with physical design teams, including reviewing synthesis/timing reports, rewriting RTL to close critical paths, analyzing timing, power, and area reports, and consulting on floor-planning for congestion/routability
• Drive timing closure from an RTL perspective, understanding core concepts like setup/hold constraints and delay sources
• Mentor junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC design best practices, particularly in areas like design methodology and problem-solving approach

Preferred Qualifications

• Formal verification ownership and expertise
• Experience with innovation or piloting new design or verification flows (e.g., AI-driven techniques)