SoC Power Design Engineer – Server – ASICS Engineering

SoC Power Design Engineer – Server – ASICS Engineering

Requirements

• Bachelor’s degree in Electrical or Computer Engineering
• ASIC frontend development
• Logic design, RTL coding, verification, synthesis, and timing closure
• Hardware description languages (Verilog, VHDL, System Verilog)
• Power-aware implementation flow, including UPF/CPF/Conformal Low Power Check
• Scripting – Perl/Tcl/Python

Responsibilities

• Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent design at SoC level
• Generate and validate power intent design (UPF) at SoC level
• Review designs and guide IP designers’ power intent design ensuring it meets SoC level low power implementation requirements
• Work with design verification in validating low power design features at SoC and IP level
• Collaborate with company CAD and vendor to enhance existing power flows and tools
• Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent QA
• Execute power-aware implementation flow, including UPF/CPF/Conformal Low Power Check
• Review IP design’s power features and power budgets/estimates
• Track IP power development through the design cycle ensuring it meets power budgets – leakage/dynamic at every milestone
• Perform power analysis/projection of SoC baseline power and deliver SoC power models to chipset
• Execute power simulation/analysis tool (PtPx/PowerArtist)

Preferred Qualifications

• Master’s degree in Electrical or Computer Engineering
• Familiarity of overall SoC Infrastructure – DDR, Busses, CPUs, I/Os and DFT Components
• Familiarity of power islands, power gating, power sequencing and multi-voltage domain design
• Power analysis familiarity in areas of clocktree, peak power, TDP, limits management