SoC Performance Architect – SoC Architecture
| Company | Qualcomm |
|---|---|
| Location | Santa Clara, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Master’s |
| Experience Level | Mid Level, Senior |
Requirements
- MS in Computer Science/Computer Engineering/Electrical Engineer with 3 years of experience in SoC performance/power modeling
- Strong grasp of the computer architecture fundamentals especially in the areas of interconnects, traffic QoS, distributed caches, coherency flows, DRAM controller and IO (PCIe) flows
- Proficient in C++ and Perl / Python
- Exposure to performance analysis and debug
- Ability to independently identify, troubleshoot and solve performance problems
Responsibilities
- Develop a SoC performance/power model for blocks such as interconnect NoCs, distributed system caches, memory controllers, IO controllers
- Verify model correctness by writing unit-tests and debugging mismatches against expectations
- Identify ideas for improving the SoC’s performance/power characteristics. Prototype idea in the performance/power model and thoroughly characterize it
- Work with architects and RTL developers to productize the improvements identified through detailed studies
- Conduct RTL performance verification. This will involve creation of verification plans and directed tests / checkers
Preferred Qualifications
- MS in Computer Science/Computer Engineering/Electrical Engineer with 6 years of experience in CPU / SoC performance/power modeling, analysis / debug
- Expertise in one or more of these functional areas: Coherent fabrics based on the AMBA CHI / AXI protocol, Memory controller designs for LPDDR5, DDR5, IO controllers and fabric bridges for PCIe / CXL / CCIX
- Strong background in building fast, accurate SoC / CPU performance models C++
- Exposure to testing and debugging performance issues in pre- and post-silicon environments
- Demonstrable experience in productizing features that improve performance/power characteristics of a design