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Server Chipset Power Engineer – CPU Engineering

Server Chipset Power Engineer – CPU Engineering

CompanyQualcomm
LocationSanta Clara, CA, USA
Salary$211900 – $349600
TypeFull-Time
DegreesBachelor’s, Master’s
Experience LevelSenior, Expert or higher

Requirements

  • Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
  • Over 10 years of experience in a combination of power estimation, modeling and optimization of CPU and/or SoCs, and at least 5 years of experience with a high-performance server chip.
  • Strong expertise in power management of a high-performance system including management of active power, idle low power and silicon/system limits.
  • Strong fundamentals in digital ASIC design and power of CMOS circuits.
  • Strong technical documentation skills, along with excellent written and verbal communication abilities.

Responsibilities

  • Develop end-to-end power modeling framework to support server use cases.
  • Perform tradeoff analysis for various workloads / usecases.
  • Identify gaps relative to targets and propose feature enhancements to meet product KPIs.
  • Collaborate with IP, SoC and Platform power and thermal engineers to optimize KPIs of the system.
  • Must have good communication skills and able to work in dynamic environment with top level engineers and technologists.

Preferred Qualifications

  • Master’s in Computer Science/Engineering, Electrical Engineering, or related field with 15 years of experience in low power design and optimization.
  • Experience in design and/or analysis of low power features at SoC, chipset and platform level.
  • Experience in hardware and software co-design of optimizations for low power features.
  • Experience in power delivery systems including multi-phase bucks and LDOs.
  • Experience in modeling peak current transients of the various IPs in the system.
  • Strong understanding of silicon test methodologies for power and thermal optimization.
  • Proven track record in hyperscale data center solutions.
  • Familiarity with high performance and low power design techniques.