SERDES Digital Design Engineer

Company	Analog Devices
Location	Centennial, CO, USA, Colorado Springs, CO, USA
Salary	$141075 – $211613
Type	Full-Time
Degrees	Master’s, PhD
Experience Level	Senior, Expert or higher

Master’s degree with 7+ years of experience or Ph.D. with 4+ years of experience is typical
Digital signal processing experience and understanding
Design and verification experience with complex digital designs using Verilog/SystemVerilog
Experience architecting and planning designs at the system level, taking conceptual product definitions and translating to design implementations
Knowledge of advanced mixed-signal SerDes transceiver architectures
Excellent knowledge in communication theory
Excellent knowledge in Matlab/Simulink and SystemVerilog real number modeling
Understanding of signal-integrity concepts, electrical channel modeling, clock and data recovery concepts, LMS adaptation algorithms
Working knowledge of analog circuit design trade-offs
Familiarity with lab measurements and silicon debug
Familiarity with C/C++ programming is a plus

Define block and system level architectures for next generation SerDes PHYs
Write block specifications and track execution at circuit-design level
Develop and maintain end-to-end Matlab/Simulink system models
Develop and run block-level DSP simulation testbenches. Apply this to system-level simulations to evaluate architectural tradeoffs.
Use Verilog/SystemVerilog to design digital signal processing blocks
Develop algorithms for adaptation and calibration of mixed-signal circuit blocks
Communicate effectively with circuit-designers and verification engineers to incorporate circuit nonidealities in system models
Work across the digital/analog boundary, including support of mixed-signal simulations and real number modeling
Work with technical leads and across multiple disciplines, including design, verification, test, product definition