Senior Staff Static Timing Analysis & Physical Design Engineer

Senior Staff Static Timing Analysis & Physical Design Engineer

Requirements

• Bachelor’s Degree in Electrical/Computer Engineering plus 3-5 years of related experience, OR a Master’s Degree in Electrical/Computer Engineering with 2-3 years related experience.
• Expertise in full-chip & sub-hierarchy integration.
• Experience integrating and taping out large designs utilizing a digital design environment.
• Good understanding of RTL to GDS flows and methodology.
• Good scripting skills in TCL/Python.
• Knowledge of Verilog.

Responsibilities

• Work with teams across various disciplines such as PD/Digital/RTL/Analog to ensure design convergence and integration in a timely manner.
• Perform Static Timing Analysis and design timing convergence and closure on multi-voltage designs using industry standard EDA tools (PrimeTime preferred).
• Work with RTL design teams to drive assembly and design closure.
• Collaborate with physical design engineers to drive designs to timing closure.
• Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.
• Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

Preferred Qualifications

• Static Timing Analysis familiarity or experience.
• Expertise in Static Timing Analysis using industry-standard STA tools (PrimeTime preferred).
• Experience driving timing closure and taping out large designs utilizing a digital design environment.
• Experience with advanced Clock Tree Synthesis and Analysis techniques.
• Experience closing timing in a Tessent DFT based design is a plus.
• Experience with Cadence Innovus.
• Experience with PrimeTime.