Senior Staff Engineer - ASIC Design

Senior Staff Engineer – ASIC Design

Bachelors in Electrical Engineering, related degree with 15+ years of experience or Masters in Electrical Engineering, Business, or comparable engineering degree with 13+ Years of Industry Experience Preferred.
3+ years of ASIC Design Experience.
Experience in designing data transfer/packetizing format
Experience in Verilog/System Verilog programming skills.
Experience in interactive and waveform debug skills.
Experience with low-power design and clock domain crossings.
Design/verification experience of link layer for utilizing UCIe Ips
Design/verification experience of data path protocol (packetizing, error correction and etc.)
Design/verification experience of ARM Cortex system using different types of BUS.
Firmware design and debugging experience
Experience with scripting such as (Python, Perl, TCL, Shell programming)

Architecting and RTL design for customized HBM buffer die
Link layer design for utilizing UCIe IPs (between HBM memory controller and UCIe IPs)
Design and implementation of NoC, and verification
Interface design for maximizing bandwidth between HBM memory and logic die
Low power design (Clock and power management), generating a UPF file and verification through multi-voltage simulations
Scope out third-party IP requirements and solicit vendors
Perform LINT and CDC checks
Static Timing analysis including generating constraints
Understanding of DFT strategies, streaming scan fabric, IEEE protocols
Experience of synthesis, DFT, functional verification, UVM verification

You’re inclusive, adapting your style to the situation and diverse global norms of our people.
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
Innovative and creative, you proactively explore new ideas and adapt quickly to change