Senior SoC Power Architect – Silicon
| Company | |
|---|---|
| Location | Mountain View, CA, USA, San Diego, CA, USA |
| Salary | $156000 – $229000 |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Senior |
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems.
- 5 years of experience in SoC power management or low power design/methodology.
- Experience with Application-Specific Integrated Circuit (ASIC) low power flows and power management concepts.
Responsibilities
- Define and drive low power solutions for Google System on a Chips (SoC) to optimize Power-Performance-Area (PPA) under peak current and thermal constraints with a focus on the CPU subsystem.
- Define power key performance indicators and SoC/IP-level power targets, guide architecture, design and implementation to achieve power targets, create power models, perform power roll ups and track power throughout the design cycle.
- Propose and drive power optimizations, both hardware and software, throughout the design process from concept to mass productization.
- Drive power-performance trade-off analysis for engineering reviews and product road-map decisions.
- Perform post-silicon characterization and productization of power features.
Preferred Qualifications
- Master’s Degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
- 8 years of experience in SoC power management or low power design/methodology.
- Experience in CPU power in mobile SoCs from CPU architecture and design to schedulers, governors and post-silicon tuning for power and performance.
- Experience with ASIC power modeling/estimation, defining power targets, power roll-ups, power/voltage domains design and low power architectures/optimization techniques.
- Experience with software and architectural design decisions on system power and thermal behavior.
- Experience with ASIC design flows from concept to post-silicon.