Skip to content
Senior Signal and Power Integrity Engineer – Hardware
| Company | NVIDIA |
|---|
| Location | Santa Clara, CA, USA |
|---|
| Salary | $136000 – $264500 |
|---|
| Type | Full-Time |
|---|
| Degrees | Bachelor’s, Master’s |
|---|
| Experience Level | Senior |
|---|
Requirements
- BS/MS-Electrical Engineering or equivalent experience.
- 3+ years of industry experience.
- SI/PI work on one or more signaling standards like PCI express, USB, SATA, HDMI, HBM, DDR5, GDDR6, LPDDR5X
- Hands on use of 3-D modeling tools like ANSYS HFSS/Q3D and 2.5-D with ANSYS SIWAVE or similar.
- Experience with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations.
- Background with a system level timing or loss budget including silicon, package and board impairments.
- Familiarity with use of VNA, TDR, DSO, ParBERT and use of applications like JMP, Matlab will be a plus.
Responsibilities
- Work on crafting creative Signal Integrity solutions to complex system design problems
- System-level signal integrity simulations of high-speed NVlinks 200Gbs+, USB-4, PCIe5, GDDR6, LP5X
- Modeling of vias, connectors, sockets and various system components in 3D EM tools.
- Design and optimize Power Delivery Network (PDN) across packages and PCBs.
- Constant improvements of SI/PI models through lab measurements
- Simulation automation, data gathering, analysis and visualization using JMP, MATLAB or similar tools.
- Opportunity to work in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit.
Preferred Qualifications
- Expertise in one or more of the high speed interface SI/PI design on any industry standard system platforms.
- Experience with lab measurements, debugging, SI lab correlation using oscilloscope/ spectrum analyzer/ VNA.
- Knowledge of circuit design, board/pkg component design, link architecture, timing budget methodologies.
