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Senior Principal IC Design Engineer

Senior Principal IC Design Engineer

CompanyMarvell
LocationAustin, TX, USA, Santa Clara, CA, USA, Boise, ID, USA
Salary$168920 – $253000
TypeFull-Time
DegreesBachelor’s, Master’s, PhD
Experience LevelExpert or higher

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
  • Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
  • PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience.
  • Must have experience with Network-on-Chip (NoC) architecture and design using Arteris FlexNoC tool.
  • Experience with general digital design microarchitecture development is a must.
  • Design/RTL experience in Verilog or SV is a must.
  • Knowledge of scripting languages, such as PERL, Python.
  • Experience with high speed, low power, and area optimized designs.
  • Experience working with multi-clock designs, DFT, resets, LEC, Lint, etc.
  • Good learning, problem solving interpersonal and communication skills.
  • Must be a team player with a strong can-do attitude.
  • Self-motivated team player able to thrive in a fast-paced engineering environment.

Responsibilities

  • Lead NoC architecture and configuration work for complex SoCs targeting multi-clock high speed designs.
  • Define the micro-architecture of SoCs including its blocks, cores, accelerators, and subsystems.
  • Work closely with the architecture, floorplanning, backend, verification, DFT, STA teams and other cross functional teams to produce high quality hardware.
  • Develop and write micro-architectural specifications of the design.
  • Implement designs using good RTL coding and low power techniques.
  • Collaborate with the backend team to close on synthesis, place and route, and timing signoff.
  • Collaborate with the verification team on pre-silicon verification tasks such as reviewing test plans, coverage closure, and full-chip simulation debug.
  • Plan, scope and time tasks with the project manager.
  • Work with post silicon group to resolve any lab issues and successfully bringup silicon.
  • Collaborate with the software team to ensure customer use cases requirements are met.

Preferred Qualifications

    No preferred qualifications provided.