Senior Principal Engineer – Verification
| Company | Marvell |
|---|---|
| Location | Santa Clara, CA, USA |
| Salary | $168920 – $253000 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Senior, Expert or higher |
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience
- 10+ years of experience in design engineering with focus on verification
- Strong experience developing complex/random verification environments using System Verilog/UVM
- Strong experience with writing and executing detailed verification test-plan
- Strong experience with scripting languages such as Python or Perl and EDA verification tools, as well as bug tracking and regression mechanisms
- Strong experience with object-oriented design and implementation
- Hands-on verification experience with subsystems such as ARM/processor, memory, networking, NoC, and Cache designs
- Experience with protocols such as PCIe, Ethernet, DDR, and HBM
- Working knowledge of C/C++ for modeling and code development to run on ARM/processors
- Excellent communication skills to interface internally and externally with all levels of the organization and to participate in problem-solving and quality improvement activities
- Demonstrates good analysis and problem-solving skills
- Must have the ability to define problems, issues, and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets
- Must have the ability to multi-task in a fast-paced environment
Responsibilities
- Work on verification of Marvell’s AI/ML, Network processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs
- Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology
- Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete
- Develop tests and tune the environment to achieve coverage goals
- Debug failures and work with designers to resolve issues
- Architecting, developing and maintaining tools to streamline the design of state-of-the-art multicore SoCs
- Experience with analysis/closure of code and functional coverage
- Technically Lead and mentor a strong verification team across multiple geographies
Preferred Qualifications
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No preferred qualifications provided.