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Senior Physical Design Engineer – Google Cloud
| Company | Google |
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| Location | Sunnyvale, CA, USA |
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| Salary | $156000 – $229000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Senior |
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Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in static timing analysis.
- Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.
- Experience in PrimeTime or Tempus TCL scripting and static timing analysis debug.
Responsibilities
- Debug and resolve common Static Timing Analysis (STA) or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
- Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
- Utilize Perl, Python, TCL, or Bash to create static timing flow automation scripts.
- Own and maintain primetime STA flows.
Preferred Qualifications
- Experience writing, reviewing and verifying complex TCL constraints for static timing analysis.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Experience working with multiple foundries.
- Knowledge of semiconductor device physics and transistor characteristics.
