Senior Photonic Layout Design Engineer

BS in Electrical Engineering (or equivalent experience)
At least 5+ years of hands-on layout design experience
Deep understanding of analog circuit layout and Silicon Photonic concepts in CMOS and SiPh technologies
Validated experience with Cadence custom circuit design tools – particularly virtuoso
Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
Ability to work optimally in a team, good interpersonal skills and positive energy
Proficiency in scripting languages like perl, python, skill etc.
Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS

Working collaboratively and multi-functionally with a multi-disciplinary team of Photonics, CMOS, Electronics, and Systems engineers
Conduct chip layout circuit design, circuit checking, and device evaluation and characterization
Responsible for chip floorplan, waveguide routing, photonic chip assembly, and back-end verification across multiple projects
Perform physical layout for mixed-signal functions like PLL’s, high speed I/O circuits, general I/O’s, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools
Work with Silicon Photonic and mixed-signal engineers to customize designs for integration in SiPh and other SERDES products
Job duties will include floor planning, custom layout and verifying against design rules and schematics
Fill, post-processing, DRC mitigation, and foundry interactions