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Senior Mixed Signal Design Validation Engineer
Company | NVIDIA |
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Location | Santa Clara, CA, USA |
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Salary | $168000 – $310500 |
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Type | Full-Time |
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Degrees | Bachelor’s |
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Experience Level | Senior, Expert or higher |
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Requirements
- A BS degree or equivalent experience with 8 years experience or higher in Electrical Engineering, Computer Engineering, or a related field.
- Solid experience in silicon bring-up and debugging, particularly for high-speed memory interfaces
- Strong understanding of Memory system and specifications.
- In-depth technical knowledge of mixed-signal circuits, analog, and digital systems, with a specific focus on high-speed memory technologies.
- Strong knowledge of signal integrity and power integrity.
- Experience with lab instrumentation, such as oscilloscopes, logic analyzers, spectrum analyzer, TDR, phase noise analyzer, signal generators and BER tester.
- Strong scripting skills in Python, C, or similar languages, with experience in Git and JMP for version control and data analysis.
- Ability to work in a fast-paced, dynamic environment that involves multiple-chip bring-ups and system validations.
- Tight-knit collaboration are required to work effectively with multi-functional teams.
- Strong problem-solving skills, with a proactive and forward-thinking approach.
Responsibilities
- Lead and drive the creation of validation test plan and test scripts for DDR I/O associated with LPDDR, GDDR, and HBM memory interfaces, ensuring all necessary required analog and digital circuits are covered.
- Conduct thorough characterization of analog, digital, and mixed-signal circuit blocks under varying conditions (process, voltage, temperature) and correlate results with simulations.
- Drive system-level validation for memory interfaces, ensuring high-speed performance and quality metrics meet the demanding standards required by our GPU and AI systems.
- Investigation validating Memory I/O circuit to understand circuit weakness paving ways circuit improvement, architecture enhancement in future products.
- Lead debugging efforts and design creative solutions to resolve unexpected bugs.
- Validate silicon performance, quality, and margins for refinement of memory interface designs.
- Develop and implement test scripts to optimize DDR I/O circuit, sub-circuits and overall system performance.
- Work closely with multi-functional teams, including Mixed signal design, PISI team, hardware, firmware, and Memory qualification engineer, to resolve issues and improve the performance for memory interfaces.
- Develop and implement tools and scripts to enhance electrical characterization and chip bring-up processes.
- Mentor and train new engineers on validation practices, encouraging a culture of excellence and continuous improvement.
Preferred Qualifications
- Need strong expertise in measurement theory and the use of test instruments, especially in the context of memory interface validation. Knowledge of other high-speed transceiver performance is a must.