Senior Micro-Architect – I/O Memory Management
| Company | Intel |
|---|---|
| Location | Austin, TX, USA, Santa Clara, CA, USA, Hillsboro, OR, USA, Worcester, MA, USA |
| Salary | $161230 – $227620 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Senior |
Requirements
- BSEE/MSEE or equivalent with 4+ Years of uArch design and MAS Development to HAS
- Proficient in RTL coding
- Must be able to debug and root cause pre-silicon volume validation failures quickly
- Knowledge in static tool failures and how to fix them in RTL
Responsibilities
- Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
- Participates in the definition of architecture and microarchitecture features of the block being designed
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features
- Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff
- Is a strong communicator that engages in technical forums/discussions to resolve issues that arise during design implementation
- Keeps silicon debug hooks in mind when coding a design
Preferred Qualifications
- Knowledge in timing reports and how to resolve timing failures in RTL
- Silicon debug experience