Senior High-Performance ASIC Timing Engineer

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience in ASIC Design and Timing
Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs
Strong background and experience in timing constraints generation, clocking, process variations and signal integrity
Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies
Familiarity with methodology and tools, logic synthesis, equivalence checking
Strong interpersonal and communication skills and ability to collaborate with cross-functional teams
Strong understanding of timing and physical design fundamentals

Develop and execute timing closure plans for NVIDIA’s next generation of high-performance IPs for CPU, GPU and SOC designs
Owning static timing analysis and convergence of high-performance designs
Responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing methodologies
Finding the right tradeoffs and balance between power/area/congestions/etc.

Familiarity with high performance mixed-signal designs, and SPICE simulation
Deep understanding of complex designs and the ability to plan and craft timing critical paths
Background and expertise in high frequency design closure at subsystem level
Ability to develop new methodologies/flows as well as workflows to aid timing convergence