Skip to content

Senior FPGA Electrical Engineer
Company | RTX |
---|
Location | Tucson, AZ, USA |
---|
Salary | $82000 – $164000 |
---|
Type | Full-Time |
---|
Degrees | Bachelor’s |
---|
Experience Level | Senior |
---|
Requirements
- Bachelor of Science in Electrical Engineering, STEM or Computer Science
- A minimum of 5 years of experience to include the following: FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
- Xilinx or Microsemi devices and flow tools
- Experience delivering FPGA/ASIC solutions to system level applications
- Hands on experience with integration and debugging of FPGA/ASIC devices
- The ability to obtain and maintain a US security clearance prior to the start date. U.S. citizenship is required as only U.S. citizens are eligible for a security clearance
Responsibilities
- Lead development of FPGA designs for all major vendors and device families including Xilinx, Altera, and Microsemi
- Collaborate with circuit card designers and systems engineers to develop requirements, architecture, modeling of algorithms, partitioning, code development, simulation, and place and route
- Verify designs against requirements using both directed test and constrained random methodologies
- Design and deliver production quality FPGA releases from initial proof of concept up to production
- Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS) test system level requirements into FPGA requirements
- Design and code in VHDL for reliability and maintainability
- Help drive projects and execute program schedules on time and budget
- Create complete documentation including requirements, verification plan, and user’s guides
Preferred Qualifications
- FPGA design experience in one or more of the following areas: Radar processing techniques, Image processing techniques for visual and infrared sensors, Embedded systems design using ARM, Microblaze, or Nios processors, Gigabit serial interfaces and multi-gigabit transceivers (MGTs), Constrained random verification in UVM using System Verilog, Verification utilizing emulation platforms, such as Veloce