Senior Engineer - Design Verification Engineering

Senior Engineer – Design Verification Engineering

Must have a Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and 2 years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
Alternatively, may have a Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and 4 years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
Demonstrated Expertise (DE) in Perl or Python scripting for data processing, data design creation, data collection, analysis, design automation tools controls, and input/output data formatting.
DE executing the full lifecycle of design/verification, including verification planning, test bench and test case development, architecting coverage and performing system debugging utilizing Cadence Xcelium simulator suite, Synopsys VCS or equivalent.
DE driving metric-driven verification, including specifying, developing, and leveraging advanced verification capabilities using System Verilog, UVM, and coverage analysis.
Demonstrated understanding of analog and digital circuits through prior work experience and coursework.
DE eliciting and communicating complex technical details before key stakeholders.

Support and accelerate product development of industry leading products involving behavioral modeling of analog circuits, spice, and mixed-signal verification; full-chip verification; and digital circuit verification.
Establish and promote the adoption of metric-driven verification best practices.
Leverage complex digital and mixed-signal circuits and create self-checking test benches to validate designs before production.
Work with analog, digital, and mixed-signal design engineers to create state-of-the-art models of mixed-signal ICs.
Apply verification methodologies to reach verification goals, including creating System Verilog simulation environments and infrastructure to verify functionality, accuracy, and performance and integrate models into full-chip simulations.
Create scripts using scripting languages to analyze simulation data, validate models, and build simulation test benches.
Correlate results with multidisciplinary teams involved in the design.
Support design teams in identifying, debugging, and resolving issues.
Assist in developing project verification strategies, planning, resource tracking, and results analysis, to ensure on-schedule product delivery.

No preferred qualifications provided.