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Senior Design Verification Engineer

Senior Design Verification Engineer

CompanyIntuitive Surgical
LocationSunnyvale, CA, USA
Salary$Not Provided – $Not Provided
TypeFull-Time
DegreesMaster’s
Experience LevelSenior

Requirements

  • Master’s Degree in Computer Engineering, Mechanical Engineering or related field and 5+ years of experience
  • Advanced knowledge of HVL methodology (UVM)
  • Expertise in HVL and HDL (SystemVerilog, Verilog)
  • Experience defining coverage space and writing coverage model
  • Team player with excellent communication skills and the desire to take on diverse challenges
  • Experience writing scripts in languages such as Perl/Python
  • Solid verification skills in problem solving, constrained random testing, and debugging

Responsibilities

  • Responsibilities include starting from Test-planning to closing verification using coverage metrics
  • Involves hands-on testbench development UVM
  • Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model
  • Write constrained random tests to cover all verification scenarios
  • Implement functional cover groups, SVA to verify randomness
  • Debugging failures, bug tracking, and analyze and close coverage

Preferred Qualifications

  • Experience with Veloce or other HW accelerators and Formal is a plus