Senior Design for Debug Architect and Methodology Engineer
| Company | NVIDIA |
|---|---|
| Location | Austin, TX, USA, Santa Clara, CA, USA |
| Salary | $168000 – $264500 |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Senior, Expert or higher |
Requirements
- Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science.
- 8+ years of meaningful work experience.
- Experience in Computer Architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches.
- Expertise in design for debug techniques and methodologies, integrated logic analyzers and/or other silicon visibility tools.
- Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup.
- Strong interpersonal skills and an excellent teammate.
Responsibilities
- Architect and implement silicon debug capabilities and infrastructure for our GPUs.
- Identify debug inefficiencies and deficiencies.
- Drive exploration of silicon debug features, specify the architecture and track execution by collaborating with many other teams at NVIDIA.
- Work closely with software, architecture, design, verification, and silicon validation teams.
- Train and mentor junior engineers and the team in silicon debug.
- Review new features from a DFD perspective to improve GPU debuggability.
- Help verify DFD hardware at full-chip level.
Preferred Qualifications
- Strong C/C++, Python, Typescript or Javascript skills.
- Good debugging and analytical skills.