Senior ARM RTL Design – Architect
| Company | Cadence Design Systems |
|---|---|
| Location | Austin, TX, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Expert or higher |
Requirements
- 10+ years of Front End design and/or verification
- BS/MS in Engineering or Computer Sciences
- Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
- Expert in RTL design (Verilog), simulators debuggers
- Hands on Experience in Synthesis, SDC creation and support PD and STA teams
- Hands on experience on CDC/RDC setup, cleanup and ownership
- Experience in C/C++ and/or Python (or scripting language)
- Experience in driving results in multi-disciplinary organization
Responsibilities
- CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP
- Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe, Ethernet, USB and other)
- Digital design and IP creation/ownership from High Level Arch Specification
- Create detailed Micro-architecture specification, work closely with the architect
- Understanding of performance measurement and refinement. Ability to work with verification/validation team to create performance verification plan
- RTL development
- Support Verification teams. Support test bench development, review verification and vPlans. Provide timely specification clarifications and debug support
- Physical design deliverables. Create functional timing constraints, synthesize RTL to ensure power and area targets are met and constraints are correct
- Plan development schedule in detail and track deliverables to ensure timely IP delivery to all consumers
- Work with multi-disciplinary teams to ensure design block/IP success for all target specifications in Silicon
Preferred Qualifications
- A Self-motivated person with good communication and design management skills
- Experience with Cadence front end toolset