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Process Integration Engineer
| Company | Applied Materials |
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| Location | Santa Clara, CA, USA |
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| Salary | $124000 – $171000 |
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| Type | Full-Time |
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| Degrees | Master’s, PhD |
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| Experience Level | Mid Level, Senior |
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Requirements
- Master’s degree or PhD in Electrical Engineering, Chemical Engineering, Materials Science, or a related field. A Ph.D. in a relevant field is preferred.
- 4-7 years of work or research experience in semiconductor processing. Proven experience in process integration, preferably R&D within a high-volume manufacturing environment.
- Deep knowledge of semiconductor module processes used in FEOL and BEOL, including lithography, etch, deposition, electroplating, CMP, wet clean, and inline and failure analysis metrology.
- Proficient in statistical data analysis and process optimization and control techniques (e.g., Design of Experiments, SPC, JMP).
- Strong communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams.
- Detail-oriented and organized, with the ability to manage multiple projects and priorities simultaneously.
Responsibilities
- Owns, manage, and drive technical programs/ project, report out timely status and interface with various stakeholders/management leading to completion.
- Develop, optimize, and own process flows, ensuring the highest level of product performance, yield, and reliability.
- Collaborate with design, process, and equipment engineers to define and implement process integration strategies and methodologies. May work with external customers/partners as well.
- Process and manage wafers/ lots through integrated lines/ process flow and collect metrology data to ensure meeting requirements such as yield, reliability.
- Collect on-wafer data, perform data analysis, and provide outcome, learnings and plan for the next process steps.
- Develop and maintain process integration documentation, including process flows, specifications, and standard operating procedures (SOPs).
- Stay updated with the latest advancements and industry trends in process integration and apply knowledge to improve processes and drive innovation.
Preferred Qualifications
- Experience of working with layout files (industry-standard such as GDS and OASIS) and familiarity of from layout design to photomask tape-out procedure is a plus.
- Knowledge of semiconductor optics principles or Si photonics components and systems is a plus.
- Knowledge of wafer-level packaging (e.g. through silicon via, hybrid bonding, wafer bonding and thinning) is a plus.
