Principal Static Timing Analysis Engineer

Principal Static Timing Analysis Engineer

Requirements

• BS in EE/CE/CS with 10+ years of experience, or MS in EE/CE/CS with 5+ years of experience
• 5 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
• Worked in the latest technology nodes, and experience in advanced timing concepts such as SI, CDC, LVF, POCV, and MIS
• Good understanding of Verilog/VHDL, along with general digital logic and architecture
• Proficient at running sub-system (ie. partition) and fullchip level timing signoff
• Proficient in UNIX, and shell based scripting
• Knowledge and Experience in both TCL and Python languages
• Have some proficiency in Synthesis and Physical Design
• Diligent, detail-oriented, and able to handle assignments with minimal supervision
• Must possess good communication skills, be a self-driven individual and a good team player
• Familiar and experienced with the balancing the trade-offs of Performance, Power, and Area

Responsibilities

• Be a Timing Sub-System/Partition or Fullchip Lead, responsible for timing closure at your hierarchical level, and all blocks within
• Work with design teams across various disciplines such as DFT, RTL, and IP in the process of iterative timing feedback and closure
• Deliver to the SoC level all necessary collateral of your sub-system/partition per the required schedule
• Conduct and adjust timing correlation between PD tools and signoff, along with participating in early feasibility studies
• Provide pushdown timing ECOs to blocks within the sub-system/partition
• Work closely with the block level PD engineers in debugging and resolving timing issues at their level, but also interface timing at the sub-system/partition level
• Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
• Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
• Responsible for managing tool independent timing constraints that will work for synthesis, place & route and static timing analysis

Preferred Qualifications

• BS in EE/CE/CS with 15+ years of experience, or MS in EE/CE/CS with 10+ years of experience
• 10 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block, sub-system (ie. partition) and fullchip level
• Leading timing closure effort with a team of engineers
• Practical experience with Synopsys Timing Tools, such as Primetime and Tweaker
• Experience in timing methodology and flow development