Principal Signal Integrity Engineer
| Company | Marvell |
|---|---|
| Location | Santa Clara, CA, USA |
| Salary | $143200 – $214500 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Senior, Expert or higher |
Requirements
- Bachelor’s degree in electrical engineering, or any other related field with 8+ years of experience; or a Master’s degree or Ph.D. in electrical engineering with 5+ years of experience.
- 5+ years of experience with HFSS, ADS, and other tools for simulations of PCBs for high-speed interfaces, including, 112G SerDes, PCIe Gen5/Gen6, DDR5, LPDDR5x, etc.
- 5+ years of experience with DC IR drop and PDN analysis for boards with ADS, Ansys, Cadence tools.
- Strong fundamentals in 3D/2D EM simulation tools and transmission line theory.
- Experienced in PCB/interposer design constraints, routing feasibility and SI/PI design considerations to identify potential future performance issues and mitigate them in the design phase.
- Excellent communication skills, both verbal and written, to effectively collaborate with cross-functional teams including, silicon, packaging, PCB design, customers, and present findings to the stakeholders.
Responsibilities
- Perform simulations for signal integrity and power integrity analysis.
- Perform hands-on high speed signal validation, analysis and correlation including de-embedding, and interconnect characterization.
- Power delivery modeling, simulation, and characterization for combined effects of die, package, board, and voltage regulators.
- Provide implementation guidelines and feedback to hardware and package design teams and occasionally to silicon design teams for electrical signal and power integrity including crosstalk, insertion loss, return loss, jitter, power supply noise, etc.
- PCB stack-up review and layer assignment for high-speed interconnects and PDN.
- Document procedures and methodologies to be adopted by other team members/teams.
Preferred Qualifications
-
No preferred qualifications provided.