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Principal Engineer – Packaging – Packaging Engineering
| Company | Qualcomm |
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| Location | Santa Clara, CA, USA |
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| Salary | $201600 – $320300 |
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| Type | Full-Time |
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| Degrees | Master’s, PhD |
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| Experience Level | Senior, Expert or higher |
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Requirements
- 10 years of experience in DDR/SerDes in Package/PCB/System Design related to Compute/Server standards
- Experience in Electromagnetics and solid background on transmission line theory & Crosstalk
- Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI and Clarity
- Experience in simulation tools such as ADS and Hspice
- Working knowledge in Cadence Allegro/APD/Sip or Mentor Xpedition
Responsibilities
- Perform package extraction for the time domain and frequency domain analysis
- Perform system-level analysis for DDR, SerDes & Mixed signal interfaces
- Provide design guidelines for the Package design
- Being able to perform system simulation and provide feedback for design optimization
- Develop design & analysis flow and automate the process
- Create technical documentation and presentations
Preferred Qualifications
- Experience in SerDes design specifications such as PCIe Gen-x, USB, UFS in Server design
- Experience in Matlab to be able to automate existing simulation flow
- Experience in programming language(c/c++) or scripting language(Perl/Python) is a plus
- Master Degree or Ph.D with 15+ years of experience
- Prior Management experience
