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Principal Engineer
| Company | Cadence Design Systems |
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| Location | San Jose, CA, USA |
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| Salary | $136500 – $253500 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Senior, Expert or higher |
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Requirements
- 8+ years of design verification experience
- Experience in mentoring junior engineers (or) leading a small team required
- BS (or higher) in EE/Computer Engineering
- Excellent knowledge of computer architecture and design verification fundamentals
- Some experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
- Experience in developing complex test bench in System Verilog using UVM methodology
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Some experience with assembly language programming required
- Excellent written and oral communication skills necessary
Responsibilities
- Verification of microprocessor cores and their peripherals
- Implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals
- Assist with developing test plans, debugging failures and analyzing coverage information
- Work closely with the RTL and EDA teams
Preferred Qualifications
- Experience with development of fully automated flows will be a plus
- Experience with Gate Level Simulations will be a plus
- Knowledge of Processor verification will be plus
