Principal Design Engineer
| Company | Cadence Design Systems |
|---|---|
| Location | Toronto, ON, Canada |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Master’s |
| Experience Level | Senior |
Requirements
- Master’s degree or higher in Electrical Engineering
- Minimum 5 years of digital design work experience
- Hands-on experience in implementing and demonstrating digital designs in FPGAs or ICs
Responsibilities
- Digital microarchitecture definition and documentation
- RTL logic design, debug and functional verification
- Understanding of digital architecture trade-offs for power, performance, and area
- Understanding of proper handling of multiple asynchronous clock domains and their crossings
- Understanding of Lint checks, UPF checks and proper resolution of errors
- Understanding synthesis timing constraints, static timing analysis and constraint development
- Understanding of fundamental physical design flows and stages
- Understanding of wireline standards and collaborating with standards experts to relate standard requirements to logic specifications
- Experience on silicon bring-up and testing of wireline IP
- Strong background in DSP and algorithms is a plus
Preferred Qualifications
- Strong background in DSP and algorithms is a plus