PLL/Clocking Design Engineer
| Company | Apple |
|---|---|
| Location | Beaverton, OR, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Expert or higher |
Requirements
- BSEE with at least 10 years of relevant experience
Responsibilities
- Leverage expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies.
- Contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Preferred Qualifications
- Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design.
- Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.
- Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
- Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics.
- Ability to design/debug RTL is a plus.
- Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving.
- A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset.
- Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.