Package/System Design Engineer – Packaging Engineering
Company | Qualcomm |
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Location | San Diego, CA, USA |
Salary | $Not Provided – $Not Provided |
Type | Full-Time |
Degrees | |
Experience Level | Junior, Mid Level |
Requirements
- Experience in IC package, SIP module and/or PCB selection, design and layout.
- Experience in Pinmap optimization of optimal package, SIP module and/or PCB designs.
- Experience in IC, package, PCB co-design for system performance optimization.
- Hands on experience with Cadence SIP and/or Mentor Xpedition.
- Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements.
- Familiar with assembly and substrate manufacturing process is a plus.
- Experience in IO + PKG + PCB SI/PI modeling, co-simulation and analysis.
- Strong knowledge in 3D/2D EM simulation tool, electromagnetic theory and transmission line theory.
Responsibilities
- Package selection, package design, and/or package EE modeling.
- Optimizing system co-design of IC-PKG-PCB die keeping in mind package footprint/height constraints, IC floor-planning, PCB, high-speed signal integrity, power distribution network, Mechanical and thermal constraints.
- IC top level floor-planning including hard macro block placement, padring, RDL and bump pattern/assignment.
- System level co-design methodology of IC, Package and PCB/Board.
- Concept analysis for new product package selection based on requirements for mechanical, thermal and electrical performance with the goal to achieve lowest system level cost.
- Package design flow methodology implementing high speed interface SI constraints for jitter, IR drop, cross-talk, and SSN specs.
- Package design flow methodology implementing power distribution network (PDN) constraints for high speed processor cores (1GHz+) including design optimization techniques at the die/pkg/PCB levels.
- Working with marketing/IC/product teams on competitive analysis and road mapping package technology for future products.
Preferred Qualifications
- Good to have 2+ years ASIC design, verification, or related work experience.