Next-Gen AI Hardware and Systems
| Company | xAI |
|---|---|
| Location | Palo Alto, CA, USA, San Francisco, CA, USA |
| Salary | $180000 – $500000 |
| Type | Full-Time |
| Degrees | |
| Experience Level | Senior, Expert or higher |
Requirements
- Proficiency in coding for accelerators, including CUDA, cutlass, HIP, ROCm, Triton, and other assembly languages or DSLs.
- Experience simulating training workloads on novel AI hardware architectures.
- Experience with compiler toolchain development and a deep understanding of the advantages and disadvantages of modular tools such as OpenXLA, MLIR, and LLVM.
- Hands-on experience with distributed training and/or high-QPS production inference.
- Deep understanding of the microarchitecture of AI accelerators and GPUs.
- R&D experience in using AI for software compiler and/or hardware design.
Responsibilities
- Optimizing front-end compilers to transform training and inference workloads into compute graphs for new AI hardware, estimating their performance.
- Writing PTX-level or lower-level codes for critical kernels to maximize performance on cutting-edge microarchitectures.
- Designing and refining new hardware architectures to push the boundaries of computational efficiency.
- Leveraging AI-driven approaches to revolutionize software compiler development and hardware design processes.
Preferred Qualifications
-
No preferred qualifications provided.