Lead Digital Verification Engineer
| Company | Cadence Design Systems |
|---|---|
| Location | Montreal, QC, Canada |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Senior, Expert or higher |
Requirements
- Thorough understanding of all aspects of modern digital verification flows
- Experience with SystemVerilog
- Working knowledge of at least one EDA verification planning tool
- Capability of leveraging scripting languages (Tcl, Perl, Python, Awk, Make, etc)
- Excellent logic debug skills
- Ability to communicate clearly with design and architecture resources
Responsibilities
- Contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure
- Work as part of a small and focused team of engineers
- Collaborate successfully with design architects and project management
- Contribute to test plan development, coverage closure, and regression failure analysis at both block and subsystem level
- Communicate with design and architecture resources to describe verification failures and contribute to issue resolution
Preferred Qualifications
- Direct experience with at least one of the following protocols: PCIExpress Gen1/2/3/4/5/6, Gigabit Ethernet, AMBA/APB/AXI/AHB, USB
- Demonstrated ability to lead small verification teams is strongly preferred