Lead Analog ASIC Systems Design Engineer
| Company | HRL Laboratories |
|---|---|
| Location | Malibu, CA, USA |
| Salary | $204665 – $262243 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Expert or higher |
Requirements
- ~70% experience in ASIC design & implementation; ~30% in system engineering and architecture.
- 15+ years of ASIC, FPGA, and firmware design experience; extensive background in analog/mixed-signal systems.
- Minimum of one full mixed-signal ASIC lifecycle, from concept to tape-out.
- Expertise in noise mitigation, power distribution network (PDN) design, and analog performance optimization.
- Strong system integration background, including architecture definition, requirements, and cross-discipline collaboration.
- Skilled communicator with experience translating research needs into engineering artifacts.
- Proven leadership in technical execution, from concept through integration and test.
- Bachelor’s, Master’s, or Doctorate in Electrical Engineering, Computer Engineering, Physics, Mathematics, or a related technical discipline from an accredited institution.
- Must hold or be eligible for a Tier 5 (T5) security clearance (formerly SSBI). U.S. Citizenship required. Continuous Evaluation (CE) enrollment may be required.
Responsibilities
- Lead systems engineering for advanced technology development, integrating hardware, software, and firmware into demonstrable prototypes.
- Drive architecture, requirements, and design definition in a model-based, agile engineering environment.
- Partner with researchers to translate experimental goals into well-defined architectures and performance-driven system requirements.
- Define and model ASIC-centric electronics systems and guide integration with broader system architectures.
- Lead Preliminary and Critical Design Reviews across multi-disciplinary teams (HW, SW, ASIC, FPGA).
- Work with design teams to optimize analog ASICs for signal integrity, timing, power, and noise-sensitive outputs.
- Decompose experimental objectives into functional block diagrams, partitioning logic across ASICs, FPGAs, CPUs, and GPUs to meet performance targets (e.g., noise, latency, thermal).
- Generate detailed interconnect and system interface diagrams for hardware and embedded platforms, defining electrical, mechanical, and data specifications.
- Identify custom or COTS IP needs for analog and mixed-signal ASIC development based on experimental functionality.
Preferred Qualifications
- Experience with multi-layer PCB design and analog/mixed-signal ASICs in low-noise environments.