Lead Advanced Microelectronics Packaging Design Engineer

Lead Advanced Microelectronics Packaging Design Engineer

Requirements

• Ability to obtain a U.S. Security Clearance
• Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science
• 5 years of experience as a substrate designer or 9+ years of professional experience with substrate layout design
• Hands-on experience with package design and proficient in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP) or Mentor Xpedition platform tools.

Responsibilities

• Designing and optimizing layout for advanced substrates of HDI IC substrate, Silicon, or LTCC substrates, considering electrical, thermal, and mechanical requirements.
• Collaborate in multi-functional discussions for package architecture and technology roadmap (partner with Silicon IC team to optimize chip Floorplan and bump placement).
• Cross-functional interface with IC design, materials, SI/PI, thermal, systems, and production teams to optimize package solutions on cost, performance, manufacturability, and reliability
• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp
• Interface with other operations functional groups such as product engineering, foundry, test, and QA
• Create and execute substrate breakout patterns for ASIC packaging
• Optimize package pinouts by evaluating system-level trade-offs – Conduct package routing, placement, stack-up, reference plane, and power distribution activities
• Conduct design feasibility studies to assess package design goals encompassing size, cost, and performance
• Develop symbols and CAD library databases using Cadence APD or Mentor Xpedition tools
• Works under minimal direction.

Preferred Qualifications

• Experience with TSV, 2D/2.5D and 3D package connection.
• Hands-on expertise of advanced and new assembly processes for flipchip, wirebond, and MCM packages
• SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters and RLGC model.
• Substrate manufacturing process, structure, design rules and material property.
• Solid understanding of high-speed interfaces, including DDR, PCIe, NAND, etc.
• Consistent track record to drive package selection through feasibility studies and drive chip Floor planning and bump assignment.
• Familiar with package design reviews and familiarity with CAM350/Valor or Calibre and CAD.
• Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs, EMI/RFI, PCB/package resonance).
• Familiar with Cadence Concept HDL for schematic review, experience in schematic capture and system integration.
• Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below
• Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers
• Understanding of layout considerations for device matching, coupling and noise isolation
• Knowledge of advanced substrate manufacturing/process
• Knowledge of failure analysis techniques on advanced node silicon products
• Conceptual knowledge of package cost structure
• Knowledge of GD&T and be able to read/comprehend mechanical drawings
• Excellent oral and written communication skills and ability to communicate across multiple disciplines with internal and external customers
• Computer proficiency and ability to use and navigate the internet and various computer software programs (e.g. Microsoft Office Suite)
• Skill and ability to collect, organize, synthesize, and analyze data; summarize findings; develop conclusions and recommendations from appropriate data sources.