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IC Packaging Principal Application Engineer
| Company | Cadence Design Systems |
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| Location | San Jose, CA, USA |
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| Salary | $123200 – $228800 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Senior, Expert or higher |
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Requirements
- Bachelor’s degree in Electrical or Electronics Engineering with 5 to 10 years related experience. Master’s preferred.
- Experience in Cadence Allegro platform tools including: Allegro Package Designer (APD+), Allegro PCB Editor, constraint management, routing, HDI.
- Design experience and industry knowledge of advanced IC Package design flows. (Ex: InFO, FOWLP, CoWoS, etc…)
- Electromagnetics, and RF related to IC Package Design is required.
- Must have excellent English written and verbal communication skills.
Responsibilities
- Support technical campaigns by delivering workshops, product demonstrations, knowledge transfer, training delivery, and onsite support.
- Analyze customer’s environment and evaluate appropriate solutions.
- Anticipate technical issues and develop creative solutions before they become a problem.
- Take technical lead on a wide range of projects.
- Understand IC package related issues and work with peers and other business groups.
- Communicate effectively with Cadence R&D, Product Engineering, Marketing, and customers.
Preferred Qualifications
- In-depth knowledge of EDA industry, Signal Integrity, Power Integrity is a plus.
- Experience with data management applications, and Cadence Allegro SKILL, Tcl is desirable.
