I/O Modeling and Characterization Engineer – ASICS Engineering

I/O Modeling and Characterization Engineer – ASICS Engineering

Requirements

• Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• 7+ years of experience in IP characterization, modeling and design verification.
• 5+ years of experience in RTL coding, Verilog and System Verilog Test benches, Design verification, IP characterization or related work experience.
• 5+ years of experience in managing, leading and mentoring a team.
• 5+ years of experience in tool evaluation, flow development with scripting tools and programming languages.

Responsibilities

• Architect and oversee the development of RTL models in Verilog for various IO configurations, ensuring scalability, reusability, and alignment with system-level requirements.
• Define and drive the verification strategy, including planning, execution, and sign-off for both behavioral and transistor-level implementations. Ensure comprehensive coverage and alignment with project milestones.
• Lead the adoption and integration of advanced verification methodologies, including SystemVerilog Assertions (SVA), power-aware verification, and formal verification techniques.
• Own and guide the debug process across IP and SoC levels, collaborating with cross-functional teams to resolve complex issues efficiently.
• Provide technical leadership in analog/mixed-signal simulation methodologies, and mentor team members in interpreting and correlating results.
• Demonstrate deep expertise in VLSI circuit design, with hands-on experience in SPICE simulations and commercial characterization tools. Drive best practices across the team.
• Review and guide the development of stimulus for timing and power characterization, ensuring alignment with I/O circuit architecture and performance targets.
• Ensure accurate modeling and interpretation of Liberty formats including NLDM, CCS, and LVF. Provide guidance on model generation and validation.
• Collaborate closely with internal stakeholders, including SoC teams, to gather requirements and deliver high-quality behavioral and timing models throughout the design lifecycle.
• Take ownership to ensure that the I/O models are successfully integrated and consumed in the RTL-to-GDSII flow.
• Provide guidance to the physical design and timing closure teams in closing timing involving I/Os. Familiarity to static timing analysis tools and flows is a must.
• Engage with EDA tool vendors to influence tool development and drive methodology improvements aligned with requirements of a cutting-edge technology nodes.
• Drive the tool evaluations and define specifications and requirements for I/O modeling and characterization, ensuring alignment with project goals and technology scaling.
• Lead the development of new methodologies and flows to support complex and scalable designs. Drive technical reviews, mentor junior engineers, and foster a culture of continuous improvement.
• Champion automation initiatives using scripting languages such as Python, Perl, or TCL to enhance productivity, consistency, and quality across the design and verification flows.

Preferred Qualifications

• Master’s degree or Bachelor’s degree in electrical engineering.