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GPU IP Verification Engineer
| Company | Intel |
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| Location | Folsom, CA, USA |
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| Salary | $121050 – $170890 |
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| Type | Full-Time |
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| Degrees | Bachelor’s, Master’s |
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| Experience Level | Mid Level, Senior |
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Requirements
- Bachelor’s degree in Electrical, Electronic Engineering, or a related field with 3+ years experience
- OR Master’s degree in Electrical, Electronic Engineering, or a related field with 2+ years experience
- Experience in digital electronics and logic design
- Proficiency in Verilog, System Verilog
- Experience in writing functional coverage points
- Knowledge in some scripting language (Perl / Python)
Responsibilities
- Performs functional verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements.
- Defines and develops scalable and re-usable IP verification plans, test benches, and architecture for verification environment to ensure coverage to confirm to graphics microarchitecture specifications.
- Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
- Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
- Collaborates with GPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
- Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
- Maintains and improves existing functional verification infrastructure and methodology.
- Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Preferred Qualifications
- Computer system architecture
- Logic validation, synthesis, and timing analysis tool
- Experience in writing functional white and black box validation test plans
- Experience in writing System Verilog Assertions
- Prior experience in pre-silicon Media Power validation domain will be a plus.
- Knowledge of simulation tools such as VCS/Verdi
