GPU Design Verification Engineer
Company | Intel |
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Location | Santa Clara, CA, USA, Hillsboro, OR, USA, Folsom, CA, USA, Phoenix, AZ, USA |
Salary | $121050 – $170890 |
Type | Full-Time |
Degrees | Bachelor’s, Master’s |
Experience Level | Mid Level |
Requirements
- Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, Physics, or related STEM field with 3+ years of experience
- OR Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, Physics, or related STEM field with 2+ years of experience
- Efficient with scripting shell, python
- IC Design and verification of complex IPs
- Computer architecture or micro controller/microprocessor
- Experience on RTL Design using Verilog/VHDL, UVM concepts
Responsibilities
- Writing specifications to describe design changes, and the intended implementation
- Coding design changes in RTL, following team coding guidelines
- Analyzing timing reports to look for alternate design approaches to meet frequency requirements
- Development of test plans, Testbench, BFMs (bus functional models), monitors, and scoreboards for assigned areas of the chip
- Test plan execution involving test writing, debugging, and driving bug closure
- Development of functional/code coverage and achieving coverage goals
- Working closely with validation engineers, design engineers, micro-architects, and other team members to ensure high quality of test plans, functional coverage, and tests that minimizes bug escapes to higher levels of validation
- Contributing to process improvements where applicable, and gaining domain expertise to be willing to independently validate effectively
- Interfacing with emulation, and software teams to ensure synergy with RTL validation
- Deliver high-quality output against deadlines and willing to work effectively in a cross-site team environment
Preferred Qualifications
- Understanding logic design and RTL
- Experience with industry standard frontend design and verification flows, tools, methodology
- PERL
- Experience in developing UVM testbench sequences, drivers, scoreboards