DSP Systems Architect

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related Professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
Programming Languages: communication system modeling, Matlab, Python, C is desirable when working with digital verification
Knowledge of AWG equipment and ability to work in the lab is a plus
Knowledgeable about the common high-speed serial data protocols PAM and system standards.
Experience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR)
Experience with FEC (RS, soft decoding, Viterbi algorithm) is a big plus.
Experience with ADC-based wireline transceivers and/or coherent DSP architectures is a plus.
Experience with high-speed/time interleaved ADC and the associated calibration algorithms is a plus.
Experience with either direct-detect/intensity modulated or coherent optical communication is a plus.

Design and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designers.
Create DSP and FEC hardware block specifications appropriate for RTL implementation.
Perform research activities in digital signal processing for SerDes and optical channels.
Work with designers to ensure circuit architecture can be efficiently implemented.
Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers.
Provide guidance on test plans for lab characterization once design comes back from fab.
Participate in chip lab bring up. Should be comfortable working with lab equipment.

Team player, willing to take on a variety of projects, good listening skills, self-motivated.