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DSP or Serdes RTL Lead Digital Design Engineer
| Company | Cadence Design Systems |
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| Location | San Jose, CA, USA |
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| Salary | $114800 – $213200 |
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| Type | Full-Time |
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| Degrees | |
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| Experience Level | Mid Level, Senior |
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Requirements
- At least 3 plus years of actual work experience in SerDes
- Thorough understanding of the end-to-end digital design flow
- Digital microarchitecture definition and documentation
- RTL logic design, debug and functional verification
- Strong background in DSP and algorithms
- Familiar with the PMA/PMD/PCS layers of the Ethernet protocol
- Understanding of digital architecture trade-offs for power, performance, and area
- Understanding of proper handling of multiple asynchronous clock domains and their crossings
- Understanding of Lint checks and proper resolution of errors
- Understanding synthesis timing constraints, static timing analysis and constraint development
- Understanding of fundamental physical design flows and stages
- Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow
- Exhibit excellent communication skills
- Self-motivated and well organized
- Substantial experience with Verilog
- Excellent logic and debug skills
Responsibilities
No responsibilities provided.
Preferred Qualifications
- Familiarity with FPGA and/or emulation platform
- Firmware development of embedded microcontroller systems
- Strong background in DSP and algorithms
