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Design Verification Engineer – Machine Learning Accelerators

Design Verification Engineer – Machine Learning Accelerators

CompanyMeta
LocationAustin, TX, USA, Redmond, WA, USA, Sunnyvale, CA, USA
Salary$173000 – $249000
TypeFull-Time
DegreesBachelor’s, Master’s
Experience LevelSenior, Expert or higher

Requirements

  • Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of hands-on experience in SystemVerilog/UVM methodology and C/C++ based verification
  • 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in one or more of the following areas along with functional verification – SystemVerilog Assertions, Formal, Emulation
  • Experience in Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  • Track record of ‘first-pass success’ in ASIC development cycles

Responsibilities

  • Work with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading Machine Learning IP’s optimized for Mixed Reality and Smart Devices and use-cases, defining verification methodologies for each of the different core IPs
  • Define, track, and lead the execution of detailed test plans for the different modules and top levels
  • Implement scalable test benches including checkers, reference models, assertions in System Verilog
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality across pre- and post-Silicon product lifecycle
  • Support hand-off and integration of developed subsystems/IP blocks into larger SOC environments
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Preferred Qualifications

  • Masters in Electrical Engineering or Computer Science
  • Experience with Design verification/validation of machine learning applications and accelerators
  • Experience with revision control systems like Mercurial(Hg), Git
  • Experience with low power design
  • FPGA/emulation debug experience
  • Experience in verification of numerical compute based designs
  • Experience with Software/Hardware Co-design at firmware, ISA, and application level