Design Verification Engineer – AI Hw
| Company | Tenstorrent |
|---|---|
| Location | Toronto, ON, Canada, Austin, TX, USA |
| Salary | $100000 – $500000 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Senior |
Requirements
- BS/MS in Electrical or Computer Engineering.
- 5+ years of ASIC/SoC verification experience, including NoC or high-throughput data movement.
- Strong SystemVerilog/UVM skills; experience building complex verification environments.
- Solid understanding of interconnect protocols (AXI, TileLink, etc.).
- Track record of executing verification plans and closing coverage.
- Scripting proficiency (Python, Tcl, etc.); familiarity with formal verification and emulation tools is a plus.
- Strong analytical and debugging skills; effective cross-functional communication.
Responsibilities
- Contribute to verification strategy for complex NoC interconnects and data pipelines.
- Build and maintain scalable UVM/SystemVerilog testbenches for protocols like AXI or TileLink.
- Create and execute test plans focused on data integrity, performance, QoS, and protocol compliance.
- Debug challenging system-level issues such as deadlocks, data flow inconsistencies, or protocol violations.
- Drive coverage closure across functional, code, and assertion metrics.
- Collaborate closely with design and software teams to resolve integration issues and improve overall verifiability.
- Evaluate and apply advanced techniques such as formal verification, power-aware simulation, or emulation.
Preferred Qualifications
- Familiarity with formal verification and emulation tools is a plus.