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Design Verification Engineer
Company | Intel |
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Location | Santa Clara, CA, USA |
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Salary | $133050 – $187840 |
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Type | Full-Time |
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Degrees | Bachelor’s, Master’s |
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Experience Level | Senior |
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Requirements
- Bachelors or MS in Electrical engineering or Computer science
- Experience of 6+ years in Design Verification at IP, SubSystem or SOC level
- Minimum 2+ years of experience in System Verilog and UVM methodology
Responsibilities
- Performs functional logic verification of an integrated SubSystem to ensure design will meet specifications.
- Defines and develops scalable and reusable block, subsystem verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
- Executes verification plans and defines and runs system simulation models to verify the design, analyze power and performance, and uncover bugs.
- Replicates, root causes, and debugs issues in the presilicon environment.
- Finds and implements corrective measures to resolve failing tests.
- Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
- Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
- Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
- Maintains and improves existing functional verification infrastructure and methodology.
- Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages and proliferates to future products.
- Candidate should be self-driven and handle the block verification independently working with cross functional teams such as design/emulation/software teams.
Preferred Qualifications
- Candidates with experience in Networking-IP (TCP-IP/ROCE/RDMA) will be added advantage