Design Verification Engineer
| Company | Meta |
|---|---|
| Location | Sunnyvale, CA, USA, San Diego, CA, USA |
| Salary | $114000 – $166000 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Junior, Mid Level |
Requirements
- Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
- 2+ years ASIC development cycle industry experience
- 2+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology
- 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in one or more of the following areas along with functional verification – SV Assertions, Formal, Emulation
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Responsibilities
- Work with researchers and architects defining verification plans for each of the different core IP
- Define and track detailed test plans for the different modules and top levels
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Preferred Qualifications
- Experience in development of UVM based verification environments from scratch
- Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
- Experience with revision control systems like Mercurial(Hg), Git or SVN
- Experience with low power design
- Experience working across and building relationships with cross-functional design, model and emulation teams
- Master’s degree in Computer Science, Computer Engineering, or a related field