Design Verification Engineer

Design Verification Engineer

Requirements

• Master’s degree in Electrical Engineering, Computer science or related field.
• Minimum 6 months of experience in Verilog, System Verilog or UVM methodology.
• Minimum 3 months of experience in Perl or Python scripting

Responsibilities

• Performs functional logic verification of an integrated SubSystem to ensure design will meet specifications.
• Defines and develops scalable and reusable block, subsystem verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
• Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.

Preferred Qualifications

• Experience with VCS or cadence simulators